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mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 1 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary 1. description M64282FP is a 128 x 128 pixel cmos image sensor with built-in image processing and analog image output tuning functions. this device can detect an image and process the image simultaneously as human retinas can . M64282FP can achieve smaller system size , lower power consumption , and more intelligent image processing functions . 2. features l single 5.0v supply l low power dissipation ( typ. 15 mw ) l positive and negative image output l edge enhancement / extraction l output level & gain tuning 3. application image input device, gaming, human interface for pc, etc. 4. block diagram start nc sin dvdd dgnd load xrst xck reset read tsw pgnd pvdd vout avdd agnd gain control logic level control edge control 16 15 13 12 11 9 14 10 1 2 4 5 7 8 3 6 pixel array 128 x 128 pin configuration (top view) outline : 16c 9-b start nc sin dvdd dgnd load xrst xck reset read tsw pgnd pvdd vout avdd agnd
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 2 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary 5. pin configuration 1 8 9 16 pin no. symbol function 1 start start input image sensing start. pulled down internally by 10k ohm. 2 nc1 non connect 3 sin data input parameter input. pulled down internally by 10k ohm. 4 dvdd digital power supply power for logic circuits. must be connected to 5.0 v digital supply . 5 dgnd digital gnd ground for logic parts. 6 load data set input parameter set enable. pulled down internally by 10k ohm. 7 xrst system reset system reset terminal. pulled up internally by 10k ohm. low active. 8 xck system clock input clock input for mux. pulled down internally by 10k ohm. 9 reset memory reset input parameter register reset. pulled up internally by 10k ohm. low active 10 read read image read image signal . 11 tsw r eserved note: don ? t connect to this pin. 12 agnd1 analog gnd ground for analog circuits. 13 avdd1 analog power supply power for analog circuits. must be connected to 5.0 v analog supply . 14 vout signal output analog image signal output in voltage. 15 avdd2 analog power supply power for analog circuits. must be connected to 5.0 v analog supply .
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 3 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary 16 agnd2 analog gnd ground for analog circuits. 6. image sensing specifications 1 item specification 1 resolution 128 x 123 2 optical system 1/4 inch 7. image sensing specifications 2 item specification 1 detectable illumination range (faceplate) 1lx ~ 10000lx* 2 exposure time range 16 sec ~ 1sec 3 system clock ( xck) 500khz 4 frame rate 10 fps ~ 30 fps 5 output voltage range ( vout) 2.0vp-p * under halogen light valve illumination 8. electrical specifications - absolute maximum ratings symbol parameter limits unit min. typ. max. dvdd digital power supply voltage 4.5 5 .0 5.5 v avdd analog power supply voltage 4.5 5 .0 5.5 v 9. electrical specifications - dc specification s symbol parameter limits unit min. typ. max. voh "h" output voltage (read) 4.5 dvdd v vol "l" output voltage (read) 0 .0 0.5 v vih "h" input voltage 2.2 dvdd v vil "l" input voltage 0 .0 0.8 v 10. ac timing requirements see the waveforms on page 5 and 6.
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 4 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary symbol parameter limits units min typ. max tcr xck cycle time 2 - - s twhx xck high pulse width 0.8 - - s twlx xck low pulse width 0.8 - - s tr xck rise time - - 0.2 s tf xck fall time - - 0.2 s tss sin setup time 0.4 - - s ths sin hold time 0.4 - - s tsl load setup time 0.4 - - s thl load hold time 0.4 - twlx-0.4 s twhl load high pulse width 0.8 - - s tsxr xrst setup time 0.4 - - s thxr xrst hold time 0.4 - - s tsr reset setup time 0.4 - - s thr reset hold time 0.4 - - s
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 5 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary (a) xck, sin timing xck sin 25% 75% t r t cr t f t whx t wlx t ss t hs (b) xck, load timing xck load t whl t sl t hl
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 6 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary (c) xck, xrst, reset timing xck xrst t sxr t hxr reset t sr t hr (d) xck, start timing xck start t sst t hst
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 7 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary 11. operation reset exposure time setup image sensing mode setup parameter setup start sensing data output end fig. 11- 1 operation flow chart figure 11-1 shows the image sensing sequence . first of all , all the registers must be reset and must be initialized to the appropriate value s . the reset sequence completes when both xrst and reset signals are set low. there are 8 sets of registers, each of
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 8 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary which consists of 8 bits of data. each input data consists of 11 bits; of these 11 bits, the first 3 bits are the address and the last 8 bits are the data. the input data is latched at the rising edge of xck when load signal is high, and the data of a register become valid at the falling edge of xck. after all register are set , start signal must be asserted. then, image sensing sequence starts at the rising edge of xck. image sensing sequence consists of two different processes : the exposing process to adjust the light intensity and the image read process to put out the image data after converting optical signal into electrical signal. after the exposure time defined by the registers 2 and 3 has passed , analog image data ( total 16k pixels ) is read out . to read image signal, read signal must be asserted . at this moment , it becomes possible to change the registers, because the registers are irrelevant to the image read sequence . once image sensing sequence starts, the chip will continue to put out image data until it is reset. 11.1. parameter register assignments symbol bit assignment operation n 1 bit exclusively set edge enhancement mode vh 2 bits select vertical - horizontal edge operation mode e 4 bits edge enhancement ratio z 2 bits zero point calibration ( set the dark level output signal to vref ) i 1 bit select inverted/non-inverted output c0, c1 8 bits x 2 exposure time o 6 bits output reference voltage ( in both plus and minus direction ) v 3 bits output node bias voltage ( vref) g 5 bits analog output gain p, m, x 8 bits x 3 1-d filtering kernel. 11.2. image acquisition modes (a) positive image set ? p ? register (b) negative image 1 set ? i ? register (c) negative image 2 set ? m ? register (optional) (d) edge extraction (v, h, 2-d) set ? n ? and ? vh ? register (e) edge extraction (1-d) set ? p ? and ? m ? register (optional) (f) edge enhancement set ? n ? , ? vh ? and ? e ? register (g) offset level output set ? 0 ? to both ? c0 ? and ? c1 ? 11.3 register assignment
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 9 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary reg. no. address 7 6 5 4 3 2 1 0 1 001 n vh1 vh0 g4 g3 g2 g1 g0 2 010 c17 c16 c15 c14 c13 c12 c11 c10 3 011 c07 c06 c05 c04 c03 c02 c01 c00 4 100 p7 p6 p5 p4 p3 p2 p1 p0 5 101 m7 m6 m5 m4 m3 m2 m1 m0 6 110 x7 x6 x5 x4 x3 x2 x1 x0 7 111 e3 e2 e1 e0 i v2 v1 v0 0 000 z1 z0 o5 o4 o3 o2 o1 o0 11.4. data load sequence xck sin load d 7 a 2 a 1 a 0 d 6 d 5 d 4 d 3 d 2 d 1 d 0 3 bit address 8 bit data 11.5. about the image processing functions a rtificial retina chip can put out positive, negative, edge extracted, and edge enhanced image in accordance with the parameter register settings. on-chip image processing is done with the 3 x 3 neighboring pixels. this chip executes subtraction between the central pixel p and the four neighboring pixels m n , ms, mw, and me (see the right figure) to realize edge extraction as shown below: vertical edge (v edge), horizontal edge (h edge), and 2 dimensional edge (2-d edge). moreover , this chip can program the weight value of the central pixel p and the other four pixels to produce edge enhanced images. p m n m s m w m e four connected neighboring pixels
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 10 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary positive v edge h edge 2-d edge edge modes output signal effective pixels v-edge extraction {2p - (mn+ms)} x a p-ms 128(h) x 121(v) 128(h) x 123(v) h-edge extraction {2p - (m w +me)} x a 128(h) x 123(v) 2d-edge extraction {4p - (mn+ms+me+mw)} x a 128(h) x 121(v) v-edge enhancement p + {2p - (mn+ms)} x a 128(h) x 121(v) h-edge enhancement p + {2p - (m w +me)} x a 128(h) x 123(v) 2d-edge enhancement p + {4p - (mn+ms+ me+ mw)} x a 128(h) x 121(v) a is the edge enhancement ratio set by ? e ? register. p and m indicate the signal value from each pixel. 11.6. register description s 11.6.1. ? n ? register (1 bit) if the ? n ? register is set, p and m registers (see 11.6.11.) are exclusively set to a specific vertical edge extraction / enhancement mode. in the case of ? h ? , for example, p register is set to 02 (hex), and m register is set to 05 (hex). if ? n ? register is set, access to p and m registers is always ignored. 11.6.2. ? vh ? register (2 bits) the ? vh ? register selects vertical, horizontal, and 2-dimensional edge extraction/enhancement operation. register setting edge mode vh1 vh0 0 0 no edge operation 0 1 horizontal edge mode
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 11 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary 1 0 vertical edge mode 1 1 2-d edge mode 11.6.3. ? e ? register (4 bits) the ? e ? register sets the edge enhancement ratio a . the most significant bit e 3 specifies edge enhancement mode or edge extraction mode: ? h ? for edge extraction mode and ? l ? for edge enhancement mode. (in the case of normal image sensing operation, e3 should be set low ) the ratio a is set as follows. 100 % means the same level as the p signal, which is the signal of the central pixel in the 3x3 processing kernel . register setting edge enhancement ratio e2 e1 e0 0 0 0 50 % 0 0 1 75 % 0 1 0 100 % 0 1 1 125 % 1 0 0 200 % 1 0 1 300 % 1 1 0 400 % 1 1 1 500 % 11.6.4. ? z ? register (2 bits) it calibrate s the zero value by setting the dark level output signal to vref. register setting calibration z1 z0 0 0 no calibration 1 0 calibration for positive signal 0 1 calibration for negative signal 11.6.5. ? i ? register (1 bit) if the ? i ? register is set to ? h ? , the output signal is inverted. if it is set to ? l ? , the signal is not inverted. 11.6.6. ? c0 & c1 ? register (8 bits x 2) both c0 and c1 registers determine exposure time ; the sum of the value of c0 register
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 12 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary and that of c1 register determines the actual exposure time. the offset level of image output can be obtained by setting both of c0 and c1 registers to 00 (the minimum exposure time) . in this case, all pixels are read out as black level (optical black). the signal output format is the same as that of the normal output image . (synchronized with the read signal.) ? c0 ? register (8 bits) register setting exposure time ( msec) 00 (hex) 0 ff (hex) 4.080 step width 16 sec step number 256 ? c1 ? register (8 bits) register setting exposure time ( msec) 00 (hex) 0 ff (hex) 1044.5 step width 4.096 msec step number 256 notice: in the case of vertical edge extraction / enhancement mode, the exposure time should be greater than 0.768 msec. 11.6.7. ? o ? register (6 bits) the ? o ? register adjusts the offset level of the signal voltage. the most significant bit o5 is the sign bit: ? h ? for plus direction, ? l ? for minus direction modulation. the offset is adjusted by 5 bit accuracy. t he maximum absolute value of the offset level is 1v. ( in the case o5 is ? h ? . ) register setting offset voltage (v) 20 (hex) 0 3f (hex) 1 step width 32mv step number 32
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 13 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary (in the case o5 is ? l ? ) register setting offset voltage (v) 00 (hex) 0 1f (hex) -1 step width -32mv step number 32 11.6.8. ? v ? register ( 3 bits ) it sets the output node voltage vref. register setting vref (v) v2 v1 v0 0 0 0 0.0 0 0 1 0.5 0 1 0 1.0 0 1 1 1.5 1 0 0 2.0 1 0 1 2.5 1 1 0 3.0 1 1 1 3.5 11.6.9. ? g ? register (5 bits) the ? g ? register sets the output gain of the image output signal . if the most significant bit g4 is ? h ? , the total gain increases by 6db. register setting total gain (db) g3 g2 g1 g0 g4 0 1 0 0 0 0 14.0 20.0 0 0 0 1 15.5 21.5 0 0 1 0 17.0 23.0 0 0 1 1 18.5 24.5 0 1 0 0 20.0 26.0 0 1 0 1 21.5 27.5 0 1 1 0 23.0 29.0
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 14 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary 0 1 1 1 24.5 30.5 1 0 0 0 26.0 32.0 1 0 0 1 29.0 35.0 1 0 1 0 32.0 38.0 1 0 1 1 35.0 41.0 1 1 0 0 38.0 44.0 1 1 0 1 41.0 47.0 1 1 1 0 45.5 51.5 1 1 1 1 51.5 57.5 11.6.10. typical register settings the following table shows the typical image acquisition modes and the register settings to each mode. mode z1 z0 n vh1 vh0 p m x e3 i posi. 1 0 0 0 0 01 00 01 0 0 inv. 1 0 0 0 0 01 00 01 0 1 h enh. 1 0 0 0 1 01 00 01 0 0 h enh. inv. 1 0 0 0 1 01 00 01 0 1 h ext. 0 0 0 0 1 01 00 01 1 0 h ext. inv. 0 0 0 0 1 01 00 01 1 1 v enh. 1 0 1 1 0 01 00 01 0 0 v enh. inv. 1 0 1 1 0 01 00 01 0 1 v ext. 0 0 1 1 0 01 00 01 1 0 v ext. inv. 0 0 1 1 0 01 00 01 1 1 2d enh. 1 0 1 1 1 01 00 01 0 0 2d enh. inv. 1 0 1 1 1 01 00 01 0 1 2d ext. 0 0 1 1 1 01 00 01 1 0 2d ext. inv. 0 0 1 1 1 01 00 01 1 1 11.6.11. p and m register settings for programmable 1-d filtering both p and m registers specify 1-d filtering kernel consisting of +1, 0 and -1 weight values. the kernel is processed with the image pixels along vertical direction. the following table shows the typical image acquisition modes and the register settings. some modes are the same as those of the table in 11.6.10 . moreover , ? negative ? output in the table is the same as the ? inverted ? output in the table in 11.6.10 . v(pm) mode works similar to the filtering pattern of (+1, -1).
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 15 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary mode z1 z0 n vh1 vh0 p m x e3 i posi. 1 0 0 0 0 01 00 01 0 0 neg. 0 1 0 0 0 00 01 01 0 1 v (pm) 0 0 0 0 0 01 02 01 0 0 v enh. 1 0 0 1 0 02 05 01 0 0 v ext. 0 0 0 1 0 02 05 01 1 0 2d enh. 1 0 0 1 1 02 05 01 0 0 2d ext. 0 0 0 1 1 02 05 01 1 0
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 16 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary 12. operation timing (1) chip reset reset timing of the chip . reset timing is synchronized with the rising edge of xck clock. (2) data input settings of the exposure time, initial value of each scanner, vref value , and gain value. data (8 bits x 8) input timing is synchronized with the rising edge of xck clock. (3) image data output image p ixel data is serially read out synchronized with xck clock. (1) chip reset xck xrst 1 clock cycle reset (2) data input sin xck load a 2 a 1 a 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d ata 0 data 7 becomes becomes valid valid
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 17 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary (3) image data output xck start read vout exposure time (0,0) (1,0) (2,0) (3,0) (127,0) (0,1) (1,1) start sensing 1st frame. start 1st frame ( start exposre ) image data output. exposure time xck start read vout (124,127) (126,127) (125,127) (127,127) end sensing 1st frame. start sensing 2nd frame. ( start signal is automatically generated inside the chip 5 clocks after the fall edge of read. )
mitsubishi integrated circuit M64282FP image sensor (artificial retina lsi) 18 / 1 8 ver. 1 .1 e 5/21 /98 mitsubishi preliminary 13. outline dimension

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